Reducing power consumption of electronic devices has become increasingly important, particularly for battery powered devices such as laptop computers, personal digital assistants, cellular phones, MP3 players and other devices. Analog-to-digital converters (ADCs) are commonly used in these types of electronic devices to receive analog signals and to transform the received analog signals to digital signals. The ADC may be a pipelined ADC that utilizes multiple stages. Power consumption of the ADCs plays an important role in the overall power consumption of the electronic device. The demand for low power consumption is particularly important for battery operated applications.
Referring now to FIGS. 1A and 1B, the receiver may generate in-phase and quadrature components. For example, in FIG. 1A an exemplary super-heterodyne receiver 14-1 is shown. The receiver 14-1 includes an antenna 19 that is coupled to an optional RF filter 20 and a low noise amplifier 22. An output of the amplifier 22 is coupled to a first input of a mixer 24. A second input of the mixer 24 is connected to an oscillator 25, which provides a reference frequency. The mixer 24 converts radio frequency (RF) signals to intermediate frequency (IF) signals.
An output of the mixer 24 is connected to an optional IF filter 26, which has an output that is coupled to an automatic gain control amplifier (AGCA) 32. An output of the AGCA 32 is coupled to first inputs of mixers 40 and 41. A second input of the mixer 41 is coupled to an oscillator 42, which provides a reference frequency. A second input of the mixer 40 is connected to the oscillator 42 through a −90° phase shifter 43. The mixers 40 and 41 convert the IF signals to baseband (BB) signals. Outputs of the mixers 40 and 41 are coupled to BB circuits 44-1 and 44-2, respectively. The BB circuits 44-1 and 44-2 may include low pass filters (LPF) 45-1 and 45-2 and gain blocks 46-1 and 46-2, respectively, although other BB circuits may be used. Mixer 40 generates an in-phase (I) signal, which is output to a BB processor 47. The mixer 41 generates a quadrature-phase (Q) signal, which is output to the BB processor 47.
An output of the BB processor is output to analog to digital converters 48-1 and 48-2, which convert analog I and Q signals to digital I and Q signals, respectively. Outputs of the converters 48-1 and 48-2 are input to a digital signal processor 49.
Referring now to FIG. 1B, an exemplary direct receiver 14-2 is shown. The receiver 14-2 includes the antenna 19 that is coupled the optional RF filter 20 and to the low noise amplifier 22. An output of the low noise amplifier 22 is coupled to first inputs of RF to BB mixers 48 and 50. A second input of the mixer 50 is connected to oscillator 51, which provides a reference frequency. A second input of the mixer 48 is connected to the oscillator 51 through a −90° phase shifter 52. The mixer 48 outputs the I-signal to the BB circuit 44-1, which may include the LPF 45-1 and the gain block 46-1. An output of the BB circuit 44-1 is input to the BB processor 47. Similarly, the mixer 50 outputs the Q signal to the BB circuit 44-2, which may include the LPF 45-2 and the gain block 46-2. An output of the BB circuit 44-2 is output to the ADCs 48-1 and 48-2 and the DSP 49.
Referring now to FIG. 2, the ADCs 48-1 and 48-2 may be pipelined ADCs. A typical pipelined ADC 55 is shown. The ADC 55 includes a plurality of stages 62-1, 62-2, and 62-3 (collectively stages 62) that are cascaded in series. Although three stages 62-1, 62-2, and 62-3 are shown, the pipelined ADC 55 may include additional or fewer stages. Some of the A/D converter stages 62 include a sample and hold module 64 that samples and holds the analog input signal Vin or the residue signal Vres from a prior stage. A low resolution A/D subconverter module 66 quantizes the held analog signal to a resolution of Bi bits where i corresponds to the current stage of the pipelined ND converter 55. The number of bits per stage Bi and/or the number of stages may be determined in part by the desired sampling rate and resolution. The output of the A/D subconverter module 66 is supplied to a low-resolution D/A subconverter module 68 that converts the resulting digital output signal back into an analog representation.
The D/A subconverter module 68 may have a resolution that is equivalent to that of the corresponding A/D subconverter module 66 of the same stage. A difference module 70 subtracts the analog output from the D/A subconverter module 68 from the voltage input Vin to generate a residue signal Vres. The residue signal Vres is equal to the difference between the held analog signal (Vin or Vres from the prior stage) and the reconstructed analog signal.
An analog interstage gain module 72 may be used to amplify the residue signal. The amplified residue signal is output to the next stage of the pipelined ADC 55. The first ADC stage 62-1 of the pipelined ADC 55 operates on a most current analog input sample while the second ADC stage 62-2 operates on the amplified residue of the prior input sample. The third stage 62-3 operates on the amplified residue output by the second ADC stage 62-2.
The concurrency of operations allows a conversion speed that is determined by the time it takes in one stage. Once a current stage has completed operating on the analog input sample received from the prior stage, the current stage is available to operate on the next sample.